1. Field of the Invention
The present invention relates to a solid-state imaging device including a sharing pixel block having a plurality of pixel transistors, and more particularly, to a solid-state imaging device configured to realize operations of reading rows performed concurrently with decimation of certain number of rows.
2. Description of the Related Art
Recently, the increase of the number of pixels in complementary metal oxide semiconductor (CMOS) image sensors has been quickly promoted. At the same time, high-speed operations of reading pixel signals, which take advantages of CMOS image sensors, have drawn attention. The two things conflicting with each other, the increase of the number of pixels and high-speed reading operations, are demanded.
As one solution for the above-described two things, operations of reading rows performed concurrently with decimation, which take an advantage in that CMOS image sensors can access any pixel therein, have been broadly used (see Japanese Unexamined Patent Application Publication No. 2004-165686). For example, referring to FIG. 13, in a case of 1/5 decimation, in an operation sequence, an operation of reading a pixel signal obtained from one row and an operation of decimating four rows are repeated. In other words, in the sequence, an operation of reading a pixel signal obtained from one row, an operation of decimating four rows, and another operation of reading a pixel signal obtained from one row, etc., are performed in this order. By using this sequence, only signals obtained from 1/5 of the total number of rows in a pixel unit can be read.
For example, in cases of digital still cameras, application examples of decimating operations include monitoring in liquid crystal monitors. When monitoring is performed, the resolution of images displayed on liquid crystal monitors does not have to be high, but operations performed in the monitoring are necessary to be performed at low power consumption. Accordingly, in such a case, decimation operations in sensors have a positive effect on the monitoring. Additionally, since the number of rows to be read is decreased using the decimation operations, high-speed reading operations can be realized in the monitoring, which is also a positive effect.
Methods of decimation of signals can be roughly classified into two types of methods: a method of one type is a method of decimating signals in units of rows; and a method of the other type is a method of decimating signals in units of columns. The present invention relates to a V-decoder circuit configured to realize decimation operations that are performed in units of rows as the above-described example. Hereinafter, “decimation” refers to decimation operations performed in units of rows.